Integrity and Reliability of Integrated CircuitS (IRIS), Phase III

Archived

DARPA - Microsystems Technology Office

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Description

DARPA is soliciting research proposals for a comprehensive exploration of the effects of extreme physical stresses on wear-out and aging mechanisms in CMOS FETs at 28nm and/or 14nm lithography node. The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out. See the full DARPA-BAA-15-47 document attached.

Who can apply

  • Unrestricted

Contact

Mr. Kerry Bernstein <br/>Program Manager
DARPA-BAA-15-47@darpa.mil

Key dates & funding
  • PostedJul 17, 2015
  • ClosesSep 4, 2015
  • Award floor$0
  • Award ceiling$0
  • CFDA12.910
Categories
Science and Technology and other Research and Development

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